1. Field of the Invention
The present invention relates to a semiconductor device which employs two or more power supply potentials, and more specifically to a semiconductor device which includes a level shift circuit transmitting a signal from a lower voltage power supply circuit to a high voltage power supply circuit.
2. Description of the Background Art
Recently, with the development of a microscopic processing technique for semiconductors, the number of transistors which can be integrated on one chip has surprisingly increased. At the same time, the restriction of voltage which can be applied to a transistor has become stricter. Further, it is inevitable to decrease a power supply potential so as to suppress the increase of consumption power following the increase of the number of transistors to be integrated. At present, in case of a MOS transistor which is used most widely, as a minimum processing dimension decreases to 0.25 xcexcm, to 0.18 xcexcm and to 0.15 xcexcm, a power supply potential decreases to 2.5 V, to 1.8 V and to 1.5V, respectively. The power supply potentials is used in the core section of an integrated circuit and is, therefore, referred to as VDD.
Meanwhile, a power supply potential VDDH of an interface section which exchanges signals with other chips is set higher than that of the core section, irrespectively of the development of the processing technique. Normally, power supply potential VDDH is set at 3.3 V. A state-of-the-art transistor cannot be employed at a voltage of 3.3 V. Though the performance is considerably lower, a transistor is used at the interface section of which gate oxide film is intentionally made thicker than that of the transistor at the core section.
The reason of setting the power supply potential of the interface section high is as follows. Since all of semiconductor devices mounted on a printed wiring board are not manufactured by the state-of-the-art processing technique and many semiconductor devices still operate according to a conventional interface standard, the change of the interface standard brings about much confusion.
Furthermore, since the interface section is provided in proximity to an input/output pin, it is necessary to increase resistance against surge breakdown of the input/output pin caused by an electrostatic force. If the thickness of the gate oxide film of a transistor in the interface section is set large, the resistance of the semiconductor device advantageously increases.
As stated above, if two or more power supply potentials are employed, it is necessary to provide a level conversion circuit (level shift circuit) which shifts the amplitude of a signal potential among circuit blocks using the respective power supply potentials.
FIG. 20 is a circuit diagram for explaining level shift sections arranged in the connection section between two circuit blocks having different power supply potentials, respectively.
Referring to FIG. 20, a core section 502 is a circuit which receives power supply potential VDD as an operating power supply potential. Core section 502 includes a NAND circuit G50 which receives signals D0 and EN, an inverter 506 which receives and inverts the output of NAND circuit G50, an inverter 504 which receives and inverts signal EN, a NOR circuit G51 which receives the output of inverter 504 and signal D0, and an inverter 508 which receives and inverts the output of NOR circuit G51.
An interface section 503 is a circuit which receives power supply potential VDDH as an operating power supply potential. Interface section 503 includes level shift circuits 513 and 515, and a driving section 519 which drives an output node D3 in accordance with data held in level shift circuits 513 and 515.
Level shift circuit 513 includes a P-channel MOS transistor P50 which is connected between a node applied with power supply potential VDDH and a node D54 and which has a gate connected to a node D51, an N-channel MOS transistor N50 which is connected between node D54 and a ground node and which has a gate receiving the output of NAND circuit G50, a P-channel MOS transistor P51 which is connected between the node applied with power supply potential VDDH and node D51 and which has a gate connected to node D54, and an N-channel MOS transistor N51 which is connected between node D51 and the ground node and which has a gate receiving the output of inverter 506.
Level shift circuit 515 includes a P-channel MOS transistor P52 which is connected between a node applied with power supply potential VDDH and a node D55 and which has a gate connected to a node D52, an N-channel MOS transistor N52 which is connected between node D55 and the ground node and which has a gate receiving the output of NOR circuit G51, a P-channel MOS transistor P53 which is connected between the node applied with power supply potential VDDH and node D52 and which has a gate connected to node D55, and an N-channel MOS transistor N53 which is connected between node D52 and the ground node and which has a gate receiving the output of inverter 508.
Driving section 519 includes an inverter 520 which has an input connected to node D51, an inverter 522 which receives and inverts the output of inverter 520, and a P-channel MOS transistor PD1 which is connected between the node applied with power supply potential VDDH and output node D3 and which has a gate receiving the output of inverter 522.
Driving section 519 also includes an inverter 524 which has an input connected to node D52, an inverter 526 which receives and inverts the output of inverter 524, and an N-channel MOS transistor ND1 which is connected between output node D3 and the ground node and which has a gate receiving the output of inverter 526.
A level shift operation will be briefly described. Data is applied as signal D0 from an internal circuit, not shown, included in core section 502. If output enable signal EN is at H level, the data is outputted from output node D3 to the outside of the chip.
If output enable signal EN is at L level, both of output transistors PD1 and ND1 are turned off and output node D3 is set in a high impedance state.
A case where L level is outputted as the data from output node D3 will be considered. In this case, output enable signal EN is set at H level (VDD) and data signal D0 is set at L level (GND). Since the output of NAND circuit G50 is at H level (VDD) on an output transistor PD1 side, N-channel MOS transistor N50 is turned on and N-channel MOS transistor N51 is turned off. Accordingly, P-channel MOS transistor P50 is turned off and P-channel MOS transistor P51 is turned on. As a result, node D54 of level shift circuit 513 is set at L level (GND) and node D51 is set at H level (VDDH). Since the gate potential of output transistor PD1 is at H level (VDDH), output transistor PD1 is turned off.
On the other hand, since the output of NOR circuit G51 is at H level (VDD) on an output transistor ND1 side, N-channel MOS transistor N52 is turned on and N-channel MOS transistor N53 is turned off. Accordingly, P-channel MOS transistor P52 is turned off and P-channel MOS transistor P53 is turned on. As a result, node D55 of level shift circuit 515 is set at L level (GND) and node D52 thereof is set at H level (VDDH). The gate potential of output transistor ND1 is at H level (VDDH) and output node D3 is driven to L level (GND).
A case where H level is outputted as the data from output node D3 will next be considered. In this case, output enable signal EN is set at H level (VDD) and data signal D0 is also set at H level (VDD).
Since the output of NAND circuit G50 is at L level (GND) on the output transistor PD1 side, N-channel MOS transistor 50 is turned off and N-channel MOS transistor N51 is turned on. Accordingly, P-channel MOS transistor P50 is turned on and P-channel MOS transistor P51 is turned off. As a result, node D54 of level shift circuit 513 is set at H level (VDDH) and node D51 thereof is set at L level (GND). Since the gate potential of output transistor PD1 is at L level (GND), output node D3 is driven to H level (VDDH).
On the other hand, since the output of NOR circuit G51 is at L level (GND) on the output transistor ND1 side, N-channel MOS transistor N52 is turned off and N-channel MOS transistor N53 is turned on. Accordingly, P-channel MOS transistor P52 is turned on and P-channel MOS transistor P53 is turned off. As a result, node D55 of level shift circuit 515 is set at H level (VDDH) and node D52 thereof is set at L level (GND). The gate potential of output transistor ND1 is at L level (GND) and output transistor ND1 is turned off.
A case where no data is outputted from output node D3 will be considered. In this case, output enable signal EN is set at L level (GND).
Since the output of NAND circuit G50 is at H level (VDD) on the output transistor PD1 side, N-channel MOS transistor 50 is turned on and N-channel MOS transistor N51 is turned off. Accordingly, P-channel MOS transistor P50 is turned off and P-channel MOS transistor P51 is turned on. As a result, node D54 of level shift circuit 513 is set at L level (GND) and node D51 thereof is set at H level (VDDH). Since the gate potential of output transistor PD1 is at H level (VDDH), output transistor PD1 is turned off.
On the other hand, since the output of NOR circuit G51 is at L level (GND) on the output transistor ND1 side, N-channel MOS transistor N52 is turned off and N-channel MOS transistor N53 is turned on. Accordingly, P-channel MOS transistor P52 is turned on and P-channel MOS transistor P53 is turned off. As a result, node D55 of level shift circuit 515 is set at H level (VDDH) and node D52 thereof is set at L level (GND). The gate potential of output transistor ND1 is at L level (GND) and output transistor ND1 is turned off.
As can be seen, if both of two output transistors PD1 and ND1 are turned off, output node D3 turns into a high impedance state.
As stated above, VDD is supplied, as H level, to the input terminals of level shift circuits 513 and 515, i.e., to the gates of N-channel MOS transistors N50 to N53, respectively. Since power supply potential VDD is higher than the threshold voltage Vthn of each of these N-channel MOS transistors, the N-channel MOS transistors can be turned on.
The gate potential of the P-channel MOS transistor, among P-channel MOS transistors P50 to P53 of level shift circuits, which is connected to the drain of the N-channel MOS transistor which is turned on, is driven to GND. Due to this, the corresponding P-channel MOS transistor becomes conductive and the potential of output node D51 or D52 is raised to power supply potential VDDH. The logical amplitude of each of output nodes D51 and D52, therefore, ranges from GND to VDDH.
In the meantime, as portable terminals have recently spread, the reduction of consumption power becomes the most significant challenge. Various techniques have been proposed particularly for reducing consumption power in a standby state. They involve, for example, a technique for changing a substrate potential, setting the threshold voltage of a transistor high and thereby decreasing leak current, a technique for supplying power to the entire core circuit through a switching transistor having high threshold voltage, turning off the switching transistor in a standby state and thereby decreasing leak current, and the like.
The most efficient method is to turn off power itself. In this case, it is necessary to turn off only the power of the core section and to hold the power of the interface section as it is in the standby state for the following reasons.
First, since there are cases where a device which is set in a standby state supplies a control signal to the other device, it is undesirable that the control signal becomes unstable. Second, if the power of the interface section is turned off, the potentials of the gate and the source of output transistor PD1 become the ground potential (GND). In this state, if the potential of a bus connected to the output node becomes H level, current is carried from output node D3 to the node which receives power supply potential VDDH through output transistor PD1. If so, not only unnecessary current is carried to the node but also the operation of the device disadvantageously becomes slow.
In this case, however, according to the conventional technique shown in FIG. 20, the potential of output node D3 becomes unstable. Namely, if power supply potential VDD of the core section is turned off, both of the gate inputs become L level and both of N-channel MOS transistors N50 and N51 are, therefore, turned off. Since node D51 tends to be set at L level by the influence of leak current and noise, output transistor PD1 may possibly become conductive.
Further, the gate inputs of N-channel MOS transistors N52 and N53 are both at L level. Due to this, if node D52 is set at H level by the influence of leak current and noise, output transistor ND1 may possibly become conductive. If both of the transistors as the output drivers become conductive, penetrating current flows in large quantities. Moreover, the potential of output node D3 becomes unstable depending on the conductive degree of the both drivers. If this device, which is in a standby state, controls the other device, malfunction disadvantageously occurs.
To keep the outputs of the level shift circuits constant even after the power of the core section is shut down, a data latch function may be added.
FIG. 21 is a circuit diagram showing a conventional technique for providing a level shift circuit section with a latch function.
Referring to FIG. 21, a core section 502A receives power supply potential VDD as an operating power supply potential, and includes a NAND circuit G52 which receives signals D0 and EN, an inverter 556 which receives and inverts the output of NAND circuit G52, an inverter 554 which receives and inverts signal D0, a NAND circuit G53 which receives the output of inverter 554 and signal EN, and an inverter 558 which receives and inverts the output of NAND circuit G53.
An interface section 503A receives power supply potential VDDH as an operating power supply potential. Interface section 503A includes a level shift circuit 513A which holds predetermined data according to the output of NAND circuit G52 and that of inverter 556, a level shift circuit 515A which holds predetermined data according to the output of NAND circuit G53 and that of inverter 558, and driving section 519 which drives output node D3 according to the data held in level shift circuits 513A and 515A.
Since driving section 519 is equal in configuration to driving section 519 shown in FIG. 20, it will not be repeatedly described herein.
Level shift circuit 513A includes an N-channel MOS transistor N60 which is connected between a node D64 and a ground node and which has a gate receiving the output of NAND circuit G52, and an N-channel MOS transistor N61 which is connected between node D51 and the ground node and which has a gate receiving the output of inverter 556.
Level shift circuit 513A also includes an inverter 560 which has an input connected to node D64 and an output connected to node D51, and an inverter 562 which has an input connected to node D51 and an output connected to node D64.
Level shift circuit 515A includes an N-channel MOS transistor N63 which is connected between node D52 and the ground node and which has a gate receiving the output of NAND circuit G53, and an N-channel MOS transistor N62 is connected between a node D65 and the ground node and which has a gate receiving the output of inverter 558.
Level shift circuit 515A also includes an inverter 564 which has an input connected to node D65 and an output connected to node D52, and an inverter 566 which has an input connected to node D52 and an output connected to node D65.
The semiconductor device according to the conventional technique has a feature in that a latch having two cross-coupled inverters is provided in each of level shift circuits 513A and 515A which apply signals to output transistors PD1 and ND1, respectively. Data is written to the latches using N-channel MOS transistors N60 to N63.
Now, a case where L level is outputted as the data from output node D3 will be considered. In this case, output enable signal EN is set at H level (VDD) and signal D0 is set at L level. On an output transistor PD1 side, N-channel MOS transistor N60 is turned on and N-channel MOS transistor N61 is turned off. As a result, node D64 of level shift circuit 513A is set at L level (GND) and node D51 thereof is set at H level (VDDH). Since the gate potential of output transistor PD1 is at H level (VDDH), output transistor PD1 is turned off.
On the other hand, N-channel MOS transistor N62 is turned on and N-channel MOS transistor N63 is turned off on an output transistor ND1 side. As a result, node D65 of level shift circuit 515A is set at L level (GND) and node D52 thereof is set at H level (VDDH). Since the gate potential of output transistor ND1 is at H level (VDDH), output transistor ND1 becomes conductive to thereby drive output node D3 to L level (GND).
Next, a case where H level is outputted as the data from output node D3 will be considered. In this case, output enable signal EN is set at H level (VDD) and signal D0 is set at H level. On the output transistor PD1 side, N-channel MOS transistor N60 is turned off and N-channel MOS transistor N61 is turned on. As a result, node D64 of level shift circuit 513A is set at H level (VDDH) and node D51 thereof is set at L level (GND). Since the gate potential of output transistor PD1 is at L level (GND), output transistor PD1 becomes conductive to thereby drive output node D3 to H level (VDDH).
On the other hand, on the output transistor ND1 side, N-channel MOS transistor N62 is turned off and N-channel MOS transistor N63 is turned on. As a result, node D65 of level shift circuit 515A is set at H level (VDDH) and node D52 thereof is set at L level (GND). Since the gate potential of output transistor ND1 is at L level (GND), output transistor ND1 is turned off.
A case where no data is outputted from output node D3 will be considered. In this case, output enable signal EN is set at L level (GND). On the output transistor PD1 side, N-channel MOS transistor N60 is turned on and N-channel MOS transistor N61 is turned off. As a result, node D64 of level shift circuit 513A is set at L level (GND) and node D51 thereof is set at H level (VDDH). Since the gate potential of output transistor PD1 is at H level (VDDH), output transistor PD1 is turned off.
On the other hand, on the output transistor ND1 side, N-channel MOS transistor N62 is turned off and N-channel MOS transistor N63 is turned on. As a result, node D65 of level shift circuit 515A is set at H level (VDDH) and node D52 thereof is set at L level (GND).
The gate potential of output transistor ND1 is at L level (GND), and output transistor ND1 is turned off. Since both of output transistors PD1 and ND1 are turned off, output node D3 turns into a high impedance state.
If power supply potential VDD of the core section is shut down while H or L level or high impedance is outputted from output node D3, the inputs of level shift circuits 513A and 515A, i.e., the gate potentials of N-channel MOS transistors N60 to N63 all become L level (GND). However, since setting values for controlling output transistors PD1 and ND1 are held by the latches, respectively, the potentials of nodes D51 and D52 are both fixed to L level (GND) or H level (VDDH). Due to this, it is possible to prevent the disadvantage of the conventional technique shown in FIG. 20 that both of the transistors as the output drivers are turned on.
Nevertheless, there are cases where after a state in which H level or L level is supplied to the other device through a control signal line is continued for a constant period, the control signal line must be released to yet another device. In that case, the output node is normally set in a high impedance state. According to the conventional techniques described with reference to FIGS. 20 and 21, however, the interface section cannot recognize output enable signal EN after power supply potential VDD of the core section is shut down. Thus, a problem that the output node cannot be set in a high impedance state disadvantageously occurs.
The fall of the potentials of input signals to the level shift circuits when the power of the core section is shut down, is quite slow compared with the ordinary fall of a signal waveform. If a control signal is inputted to force the output node to be set in a high impedance state so as to solve the above-stated disadvantages, this control signal competes with the input signal in the interface section and penetrating current sometimes flows in the interface section. Further, after the power of the core section is shut down, input signals to the level shift circuits both turn into a high impedance state, so that erroneous data may possibly be set by the influence of noise and the like.
It is an object of the present invention to provide a semiconductor device capable of setting an output node in a high impedance state even if the power of a core section is turned off and capable of decreasing penetrating current when the output node is changed from an active state to a high impedance state.
It is another object of the present invention to provide a semiconductor device capable of preventing output malfunction caused by the influence of noise generated in an input signal to a level shift circuit if the power of a core section is shut down.
In short, this invention provides a semiconductor device which includes an internal circuit and an interface section.
The internal circuit receives a first power supply potential as an operating power supply potential, and outputs a first internal signal. The interface circuit receives, as an operating power supply potential, a second power supply potential capable of being maintained in an active state even if the first power supply potential is set in an inactive state, and drives an output node in accordance with the first internal signal. The interface circuit includes a first level conversion circuit and a driving section. The first level conversion circuit includes: a first holding circuit holding one of a first logical value and a second logical value complementary to the first logical value; a first write circuit writing one of the first and second logical values to the first holding circuit in accordance with the first internal signal; and a second write circuit writing the second logical value to the first holding circuit in accordance with an enable signal. The driving section drives the output node if the first holding circuit holds the first logical value, and turns into a high impedance state with respect to the output node if the first holding circuit holds the second logical value.
According to another aspect of the present invention, this invention provides a semiconductor device which includes an internal circuit and an interface section.
The internal circuit receives a first power supply potential as an operating power supply potential, and outputs an internal signal. The internal circuit includes a first pulse generation circuit activating the internal signal for a predetermined period in accordance with transition of a data signal. The interface circuit receives, as the operating power supply potential, a second power supply potential capable of being maintained in an active state even if the first power supply potential is set in an inactive state, and drives an output node in accordance with the internal signal. The interface circuit includes a first level conversion circuit and a driving section. The first level conversion circuit includes: a holding circuit holding one of a first logical value and a second logical value complementary to the first logical value; and a write circuit writing one of the first and second logical values to the holding circuit in accordance with the internal signal. The driving section drives the output node if the holding circuit holds the first logical value, and turns into a high impedance state with respect to the output node if the holding circuit holds the second logical value.
According to yet another aspect of the present invention, this invention provides a semiconductor device which includes a core section and an interface section.
The core section receives, as operating power supply potentials, a first power supply potential and a second power supply potential, the second power supply potential capable of being maintained in an active state even if the first power supply potential is set in an inactive state. The core section includes a first internal circuit and a second internal circuit. The first internal circuit receives the first power supply potential as the operating power supply potential, and outputs an internal signal. The second internal circuit operates in accordance with the internal signal. The second internal circuit includes a level conversion circuit converting a logical amplitude of the internal signal. The level conversion circuit includes: a holding circuit holding one of a first logical value and a second logical value complementary to the first logical value; and a write circuit writing one of the first and second logical values to the holding circuit in accordance with the internal signal. The interface circuit receives a third power supply potential as the operating power supply potential, and mediates data communication between the core section and an outside of the semiconductor device.
According to still another aspect of the present invention, this invention provides a semiconductor device which includes an internal circuit and an interface section.
The internal circuit receives a first power supply potential as an operating power supply potential, and outputs an internal signal. The interface circuit receives, as the operating power supply potential, a second power supply potential capable of being maintained in an active state even if the first power supply potential is set in an inactive state, and drives an output node in accordance with the internal signal. The interface circuit includes: a level conversion circuit converting level of the internal signal, and a driving section. The level conversion circuit includes: a level conversion section converting the level of a signal received at an input, and outputting the level-converted signal; and an input signal switching section applying the internal signal to the input of the level conversion section when a mode setting signal is active, feeding back an output of the level conversion section to the input of the level conversion section and separating the internal signal from the input of the level conversion section when the mode setting signal is inactive. The driving section drives the output node if the output of the level conversion circuit corresponds to a first logical value, and turns into a high impedance state with respect to the output node if the output of the level conversion circuit corresponds to a second logical value.
Therefore, the main advantage of the present invention is in that even if the power supply of the internal circuit is shut down for reducing consumption power while the output node outputs H level or L level, the output state of the output node can be maintained and the output node can be then set in a high impedance state. As a result, a bus or the like connected to the output node can be released.
Another advantage of the present invention is in that if the output node is set in a high impedance state, it is possible to prevent the competition of potentials between the nodes due to the slow falling rate of the potential of an input signal into each level shift circuit, to prevent penetrating current and to thereby ensure stable operation.
Yet another advantage of the present invention is in that even if the lower power supply potential out of a plurality of power supply potentials employed in the core section is shut down for reducing consumption power while each level shift circuit outputs H level or L level, the level shift circuit holds data and the output of the output node does not become unstable.
Still another advantage of the present invention is in that if the power supply of the internal circuit is shut down, an input signal into each level shift circuit is separated from an output from the internal circuit. Due to this, inverted data is not set to the level shift circuit by the influence of noise and the like. In addition, since no pulses are generated, delay circuits become unnecessary, whereby the number of constituent elements and consumption power can be greatly decreased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.